This invention relates to integrated circuits, and more particularly, to integrated circuits with transistors having high K dielectrics and short gate lengths.
As dimensions of integrated circuit transistors continue to shrink, gate dielectrics of the transistors have become thinner and shorter as well. The thinner gate dielectrics are generally made from materials known as high K dielectrics because they are made from materials having dielectric constants greater than that of silicon oxide. These high K materials increase the capacitive coupling between the gate of the transistor and the channel. This increased coupling has become necessary because the background well doping in which a transistor is formed has increased. The increase in well doping is due to the need to avoid punch-through between the source and the drain of the transistor. Increased doping of the well caused it to be more difficult to invert the channel between the source and drain. Thus, the result was the need for increased coupling between the gate and the channel in order to achieve the needed inversion.
The gate electrode is not only coupled capacitively to the channel region but also to the source/drain extension regions of the transistor. A high gate-to-channel coupling is desirable, but a high gate-to-extension coupling is not desirable. The thin gate dielectric and its high K characteristic thus result in undesired increased capacitance between the gate and the source/drain extensions. This capacitance is commonly known as Miller capacitance. Miller capacitance has the adverse effect of making the transistor operate more slowly when it is switching. For example, in a digital circuit application, it may be important for the transistor to turn on and off very quickly, so having a transistor with low Miller capacitance is very important.
To reduce Miller capacitance in a transistor having a high K dielectric and short gate length, it may be possible to reduce the overlap between the source/drain extensions and the gate. One technique to do this has been to provide a film around the gate prior to a source-drain implant step. This film acts as spacer to offset the source/drain extension implant from the gate so that with subsequent processing the diffusion of the implant would not extend as far under the gate as had been typical. This additional film also complicates the processing.
Another technique to reduce overlap is to reduce the amount of lateral diffusion of the implant. Lateral diffusion is reduced by decreasing the anneal time and/or temperature. However, decreased anneal time and/or temperature may cause reduced dopant activation. Thus, there is a need for short gate length transistors with reduced Miller capacitance for high speed switching applications.